Today's semiconductor memory systems employ multiple subarrays of memory storage units closely packed together. Each subarray is segmented into multiple rows or words, with each word containing multiple data storage cells. Each data storage cell accommodates a bit of data. Typically these multiple subarrays of memory storage units are coupled together by numerous common interconnections, including a common system data bus. During a read access, a system control circuit oversees selection of a particular data storage cell and transfer of that cell's data to the common system data bus for output from the memory system. Upon receipt of a read command (RC) from the control circuit, data to be output is latched from the system data bus into associated multiple data output latches.
The read command (RC) is generated by the control circuit in response to an externally-generated read clock signal. Without added delay, the read command (RC) is generated long before data on the system data bus becomes valid. Since the system data bus is common to all subarrays, it has significant associated capacitance which in the case of a low state signal must be dissipated before the data signal can become valid. In such a case, the cross-coupled connections of the data output latches are unnecessarily exposed to the stored charge on the system data bus (rather than a valid low state signal) and possibly unnecessarily switched to the wrong data value. When valid data does appear on the system data bus (which in this example is assumed to be a low state), a wrongly switched latch would again have to change state. Such double switching undesirably increases noise and power dissipation within the memory system. Traditionally, the problem has been addressed by buffering the read command (RC) through a fixed delay which the circuit designer determines is sufficient to ensure that valid data has developed on the system data bus. Clearly, the fixed delay solution can unnecessarily lengthen the read access cycle.
Thus, a need exists within the semiconductor memory technology for a control circuit and control process which generate a read command (RC) substantially simultaneous with development of valid data on the system data bus in response to positive information indicative of the instant of valid data development.